fetch cycle

fetch cycle
цикл выборки
первая стадия обработки машинной команды процессором - извлечение команды из кэш-памяти или из ОЗУ в регистр команд (instruction register) и подготовка её к декодированию.

The instruction needs to be fetched, decoded and then results need to be written back to main memory or the register file. — Нужно выбрать команду, декодировать её, а затем результат выполнения записать в оперативную память или регистровый блок см. тж. fetch-execute cycle, fetch packet, fetch time, instruction decoder, prefetcher


Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. . 1998-2007.

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Смотреть что такое "fetch cycle" в других словарях:

  • Instruction cycle — An instruction cycle (sometimes called fetch and execute cycle, fetch decode execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what …   Wikipedia

  • Branch predictor — In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. This is called branch prediction. Branch predictors are… …   Wikipedia

  • Cycles per instruction — In computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is a term used to describe one aspect of a processor s performance: the number of clock cycles that happen when an instruction is… …   Wikipedia

  • Cycles Per Instruction — In computer architecture, Cycles per instruction (clock cycles per instruction or clocks per instruction or CPI) is a term used to describe one aspect of a processor s performance: the number of clock cycles that happen when an instruction is… …   Wikipedia

  • PowerPC 600 — The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was… …   Wikipedia

  • цикл выборки — — [Е.С.Алексеев, А.А.Мячев. Англо русский толковый словарь по системотехнике ЭВМ. Москва 1993] Тематики информационные технологии в целом EN fetch cycle …   Справочник технического переводчика

  • Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… …   Wikipedia

  • CPU cache — Cache memory redirects here. For the general use, see cache. A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the… …   Wikipedia

  • Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… …   Wikipedia

  • R800 — The R800 is the central processing unit used in the MSX Turbo R home computer. The R800 was designed by the ASCII company of Japan, and the goals were to have the fastest CPU possible, while maintaining compatibility with old MSX Zilog Z80 based… …   Wikipedia

  • Joel McCormack — is the designer of the NCR Corporation version of the p code machine which is a kind of Stack machine popular in the 1970s as the preferred way to implement new computing architectures and languages such as Pascal and BCPL. The NCR design shares… …   Wikipedia


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